EDAxpert is created by experts from EDA tools and digital design methodologies.
See who they are and their achievements.
I am an independent consultant with over 20 years of experience in System On Chip design methodology and tool flow development with major semiconductor companies.
I have considerable experience in RTL assembly, RTL design and verification, IP management, IP quality checking, DFT, physical implementation, and many other areas of the SoC ecosystem like IP-XACT, power, data management and flow monitoring.
I have proven communication skills and am very comfortable working in a complex multicultural environment, having supported large international design teams with many diverse EDA technologies.
Innovation, flexibility and trust are key principles which guide my professional life.
I live near Grenoble in France, and I'm available for missions in France and Europe.
For more information on me you can also look at my linkedIn profile
Here are some major EDA related activities I did manage:
- Design platform used by 100+ designers automating the flow to generate and package front-end view for soft IPs. This includes IP-XACT packaging, RTL checking, logical/physical synthesis, DFT insertion and checks, data packaging and many more steps needed to deliver a certified IP package with maximum quality.
- Benefits: productivity improvement (TAT divided by 5), quality improvement (sharing best practices and quality metrics), standardization across teams.
- General purpose design builder targeting various EDA tools (from verification to implementation) and able to cope with various low level data management tool.
- Benefits : productivity (push button design builds for most of tools, including libraries, corners, etc ...). Interoperability between teams even if they use different data management tools.
- Automation of logical/physical synthesis & DFT scripts for IP & SoC design.
- Benefits : Runtime optimization, consistent quality across teams, shared design standards (clocks, constraints, DFT).
- Introduction & deployment of IP-XACT based SoC (RTL) and VSoC (TLM) assembly.
- Benefits : Correct by construction design assembly, reuse/consistency between SoC design and Virtual SoC prototyping.
- Development & Introduction of automated RTL restructuring flow.
- Benefits : Enable late change in design hierarchy to cope with timing/area/power constraints without the need to rework the RTL.
- EDA budget management (> 20M$ per year) and license management for a major division of a leading semiconductor company.
- Management of a design support and methodology team helping various design teams in their day to day usage of tools from Synopsys, Cadence, Mentor, Atrenta, Dassault system, and many other vendors. Includes flow definition, training, issue management, documentation, workaround development and interface with EDA vendors.
- Multiple partnerships with EDA vendor including Physical synthesis with Synopsys, IP-XACT assembly with Synopsys and Atrenta, Design Data management with MatrixOne/Dassault, IP Quality checking with Satin-IP technologies, RTL restructuring with Atrenta.
- Contribution to IP-XACT Accellera Standard Extension working group (physical design planning extensions).
Here are some publications I did contribute to:
- DAC user track 2014: Effective RTL Coding Rules to Avoid Simulation Shoot-Thru
- DASIP 2012 : Impact of High-level Transforms for High-level Synthesis for Motion Detection Algorithm,
- DAC user track 2012 : RTL Restructuring With Atrenta GenSys
- DAC user track 2009 : Enabling IP Quality Closure at STMicroelectronics with VIP Lane
- SNUG 2006 : 65 nm SoC design based on an emerging standard: SPIRIT
- DATE 2006 : Industrially proving the SPIRIT consortium specifications for design chain integration
- EEtimes 2002 : Data management allows collaborative engineering
- PhD thesis in 1998 with Paris 6 University : A test methodology for integrated circuit, based on a structural partitioning with minimum overlap
- Co-winner in 1994 of the “SEYMOUR-CRAY – SPECIAL TEAM AWARD” for the development of the ALLIANCE CAD System for VLSI designs, Paris, France